This invention relates generally to methods of forming alternating phase shift circuitry fabrication masks, to methods of forming circuitry fabrication masks having a subtractive alternating phase shift region, and to alternating phase shift masks.
In semiconductor manufacturing, photolithography is typically used in the formation of integrated circuits on a semiconductor wafer. During a lithographic process, a form of radiant energy such as ultraviolet light or electron beam is passed through a mask/reticle and onto the semiconductor wafer. The mask contains light restricting regions (for example totally opaque or attenuated/half-tone) and light transmissive regions (for example totally transparent) formed in a predetermined pattern. A grating pattern, for example, may be used to define parallel-spaced conductive lines on a semiconductor wafer.
The wafer is provided with a layer of energy sensitive resist material, for example photosensitive material commonly referred to as photoresist. Ultraviolet light passed through the mask onto the layer of photoresist transfers the mask pattern therein. The photoresist is then developed to remove either the exposed portions for a positive resist or the unexposed portions for a negative resist. The remaining patterned resist can then be used as a mask on the wafer during a subsequent semiconductor fabrication step, such as ion implantation or etching relative to layers on the wafer beneath the resist.
Advances in semiconductor integrated circuit performance have typically been accompanied by a simultaneous decrease in integrated circuit device dimensions and in the dimensions of conductor elements which connect those integrated circuit devices. The wavelength of coherent light employed in photolithographic processes by which integrated circuit devices and conductors are formed has typically desirably been smaller than the minimum dimensions within the reticle or mask through which those integrated circuit devices and elements are printed. At some point, the dimension of the smallest feature opening within the reticle approaches the wavelength of coherent light to be employed. Unfortunately, the resolution, exposure latitude and depth of focus in using such reticles and light decreases due to aberrational effects of coherent light passing through openings of width similar to the wavelength of the coherent light. Accordingly as semiconductor technology has advanced, there has traditionally been a corresponding decrease in wavelength of light employed in printing the features of circuitry.
One approach for providing high resolution printed integrated circuit devices of dimensions similar to the wavelength of coherent light utilized employs phase shift masks or reticles. In comparison with conventional reticles, phase shift masks typically incorporate alternating thicker and thinner transparent regions within the conventional chromium metal-on-glass reticle construction. These shifter regions are designed to produce a light transmissive substrate thickness related to the wavelength of coherent light passing through the phase shift mask. Specifically, coherent light rays passing through the light transmissive substrate and the shifter regions have different optical path lengths, and thus emerge from those surfaces with different phases. By providing light transmissive shifter regions to occupy alternating light transmitting regions of the patterned metal layer of a conventional phase shift mask of the Levenson type, adjacent bright areas are formed preferably 180xc2x0 out-of-phase with one another. The interference effects of the coherent light rays of different phase provided by a phase shift mask form a higher resolution image when projected onto a semiconductor substrate, with accordingly a greater depth of focus and greater exposure latitude.
Where etching is used to form the alternating phase shift regions, unfortunately, such etched spaces transmit less light than adjacent unetched spaces due to total internal reflection along the sidewalls. Accordingly, the resultant image can consist of unevenly spaced lines/devices inspite of equal spacing on the mask.
A number of different techniques have been proposed to balance the transmission of etched versus adjacent unetched spaces. Such include blanket wet etching the entire reticle to enlarge both the etched and unetched spaces to undercut the chrome layer as well as widen the base of the quartz material. Unfortunately, isotropically wet etching a reticle can create large masking layer overhangs.
Another method includes selectively wet etching just the phase shift regions while masking the non-shifted regions. Another method involves dry etching both shifted and non-shifted regions. Unfortunately, this can reduce the transmission of light passing through both the shifted and non-shifted regions, thus degrading the image quality.
Another method utilized in an effort to overcome the above-described problem is known as xe2x80x9cdata biasingxe2x80x9d. Here, the spacing on the mask between features is modified from that desired on the wafer such that the resultant desired intensity is achieved on the wafer and thereby the desired circuitry pattern is created. Yet, circuitry designs are typically only biased in increments and not to dimensions between the increments. Accordingly, designs typically need to xe2x80x9csnapxe2x80x9d to a grid in order for the geometries to be defined. For instance, a polygon can be defined by sets of coordinates located on a grid. As the grid shrinks, the polygon can be defined more precisely thus increasing the resolution of the design. However, the amount of data defining the design can, and usually does, increase as well. Yet it is desirable to keep data file size to a minimum to minimize subsequent problems, such as computers running out of memory while manipulating them.
For example, engineers typically first define the grid in the design software or CAD program. One common CAD program is Design Framework II (DF2) sold by Cadence Design Systems, Inc. of Sunnyvale, Calif. and an example typical grid size is 0.05 um drawn which translates to 0.02 um for a 4xc3x97 reticle. Physical verification programs, such as Design Rule Checkers (DRC""s) and Optical Proximity Correction (OPC) also use grids, usually the same size as the original layout. For example, Mentor Graphics of Wilsonville, Oreg. sells DRC and OPCprograms, both under the name Calibre. Also, tools which convert the data from a CAD format to write tool formats, commonly referred to as fracturing, obey grid constraints. An example common fracture program is Computer Aided Transcription Software (CATS) sold by Transcription Enterprises Limited of Los Gatos, Calif. Then finally, reticle write tools accept the data with the predetermined grid. However, today""s write tools also typically have a finite resolution which means that they are only capable of writing patterns at specified minimum grid sizes. For example, a writing tool may be able to resolve the spacing of 0.9 micron, 0.94 micron and 0.98 micron, but not be able to resolve between any of these values. Accordingly, the data with the predetermined grid also should fall within the resolution specification of the tool. So, designers choose grid sizes that compromise between design resolution and data file sizes, while not exceeding the manufacturing capability of the write tool. Yet, if the data biasing simulation software or other empirical data directs the biasing to be, for example, 0.92 micron to achieve resultant circuit resolution of 0.94, the particular writing tool is not able to create the desired 0.92 value on the mask.
Example prior art alternating phase shift mask fabrication techniques and masks are described in Uwe A. Griesinger et al., Transmission and Phase Balancing of Alternating Phase Shifting Masks (5xc3x97)xe2x80x94Theoretical and Experimental Results, SPIE99 #3873-36, pp. 1-11; and in Christophe Pierrat et al., Phase-Shifting Mask Topography Effects on Lithographic Image Quality, SPIE Vol. 1927 Optical/Laser Microlithography VI (1993), pp. 28-41.
The invention comprises methods of forming alternating phase shift circuitry fabrication masks, methods of forming circuitry fabrication masks having a subtractive alternating phase shift region, and alternating phase shift masks. In one implementation, a method of forming an alternating phase shift circuitry fabrication mask incudes combining circuitry pattern is data biasing and wet undercut etching of light transmissive substrate material adjacent phase shift regions of the mask in fabricating the mask.
In one implementation, a method of forming an alternating phase shift circuitry fabrication mask includes combining circuitry pattern data biasing and wet undercut etching of light transmissive substrate material adjacent phase shift regions of the mask effective to achieve a first data biased pattern when using the mask to fabricate circuitry of a desired circuit pattern on another substrate. The first data biased pattern has at least some first resolution spacing falling between a discrete finite resolution spacing of which a writing tool used to fabricate the mask is capable of achieving.